Friedrich Hapke, Director of Engineering for Tessent Solutions, Mentor Graphics, received the Bob Madge Innovation Award at the 2015 IEEE International Test Conference (ITC) for Cell-Aware Test. This ...

Physical defects like shorts and opens may occur during any step of the fabrication process. Well-known fault models like stuck-at (SA), 1 transition (TR), 2 N-detect (ND), 3 gate-exhaustive (GE), 4 ...

Early results of using device-aware testing on alternative memories show expanded test coverage, but this is just the start. Once the semiconductor industry realized that it was suffering from device ...

The IDDQ test relies on measuring the supply current (I DD) of an IC’s quiescent state, when the circuit isn’t switching and inputs are held at static values. Test patterns are used to place the ...

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.