Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...
EDN

IC Performance: Challenges in Layout with CMOS Technology Nodes

Editor’s note: I am pleased to bring you an important technical blog by Fernando Lavalle, a Ph.D. student at Texas A&M University and his colleague, Suraj Prakash, who have been working and studying ...
Electronic Design

CMOS Circuit Design, Layout, and Simulation, Second Edition

CMOS technology has dominated the IC business for the last 25 years and will continue to do so for another 25 years, according to the author of CMOS Circuit Design, Layout, and Simulation. He explains ...
EDN

Electrically Correct Analog Layout

Analog IC layout relies on the schematic as a starting point, conveying not only information about the connectivity of the devices in the circuit, but also the design intent. Traditional approaches ...
Design-Reuse

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...
Design-Reuse

RF CMOS challenges in SoC Implementation

Designers creating the analog/RF portion of system-on-chip designs need considerable additional support from the foundry. Take one simple component, the inductor, to illustrate the depth of these ...
Semiconductor Engineering

The Future Of MEMS Design: Making MEMS Design More Like CMOS Design

MEMS-based component suppliers want to rapidly ramp their designs into high-volume production. This demand is driving MEMS suppliers to focus on ways to more efficiently re-use established process ...