The Questa One Agentic Toolkit works seamlessly with the Fuse (TM) EDA AI system, Siemens' agentic and generative framework for electronic design automation, providing customers who want a fully ...

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Enthusiast and frequent leak-spotter Gray (@Olrak29_ on Xwitter) spied a fresh job posting from Intel that's got the tight-knit community of hardware nerds buzzing with speculation on Chipzilla's ...

Its use results in faster development, cleaner testbenches, and a modern software-oriented approach to validating FPGA and ASIC designs without replacing your existing simulator.

It appears that Intel could be making plans to ditch its current hybrid core design, and return to a Unified Core Design for ...

Editor Bill Wong talks with Mentor’s David Wiens about its unique “shift-left” PCB design verification platform for early prototyping and reduced re-spins. A “shift-left” PCB design verification ...

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, ...

It’s often said that “the secret to a good marriage is good communication” but it’s equally true that good communication is the secret to a successful IP or system-on-chip (SoC) project. Such projects ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Aparna Mohan pioneered a groundbreaking verification methodology for security-critical semiconductor designs that has transformed how the industry approaches security verification, yielding ...