Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
EDN

Formal-based methodology cuts digital design IP verification time

When we talk about the signoff of digital IP, we are referring to the full verification of a block. Every feature listed in a device’s datasheet requires verification. Furthermore, every register ...
Semiconductor Engineering

Verification As A Flow (Part 2)

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, ...
Semiconductor Engineering

Verification As A Flow (Part 1)

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...
mccormick.northwestern.edu

COMP_ENG 387: Real-Time Digital Systems Design and Verification with FPGAs

This course covers the systematic design of real-time digital systems and verification techniques using field-programmable gate arrays (FPGAs). The course presents a top-down design methodology, where ...
Electronic Design

11 Myths About Verification IP

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...
Design-Reuse

Accellera Approves Universal Verification Methodology (UVM) Standard

Open-Source SystemVerilog base class library implementation and User Guide accompanies the UVM Class Reference Manual; Workshop set for Monday, Feb. 28 at DVCon NAPA, Calif., February 21, 2011 — ...
Design-Reuse

Mentor Graphics Adds Memory Models to Create Industry's First Complete UVM SystemVerilog Verification IP Library

WILSONVILLE, Ore., Feb. 29, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced availability of the first entirely native UVM SystemVerilog memory verification IP library for all ...
EDN

How formal verification saves time in digital IP design

It is well known that the task of verification looms large in the design of digital IP, as well as the design of SoCs. The target is to reach 100% for both RTL code and functional coverage, minimizing ...