EDN

Introduction to Formal Verification

Formal verification is an automatic checking methodology that catches many common design errors and can uncover ambiguities in the design. Formal verification is the process of verifying the ...
EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
Semiconductor Engineering

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to ...
Design-Reuse

Using in-design physical verification to reduce tapeout schedules

. Tadahiko Yamamoto is Chief Specialist, Design Methodology Development Group, at Toshiba Corp. . Norikazu Ooishi is Specialist, Design Methodology Group, at Toshiba Corp. Physical designers moving to ...
Semiconductor Engineering

The Process Design Kit: Protecting Design Know-How

Once upon a time, integrated circuits (ICs) were built by the same companies that designed them. The design of an IC was tightly integrated with the manufacturing processes available within each ...
Electronic Design

Production-Grade AI Arrives in EDA for Analog Design and Verification

The limitations of traditional SPICE simulations. Role of production-grade AI in transforming EDA. Applications of AI in day-to-day engineering. The future of AI in analog design. In the realm of ...
SiliconANGLE

Cadence announces ChipStack ‘Super Agent’ system for chip design and verification

Integrated circuit and electronic hardware design company Cadence Design Systems Inc. today announced the release of an artificial intelligence “Super Agent” designed to transform front-end silicon ...
Embedded

Cadence hails EDA 2.0 with unified data and AI driven verification

Cadence Design Systems has launched a data platform that pulls in the masses of data being collected by EDA tools, and is using this to enable a suite of AI-driven verification applications that aim ...
Design-Reuse

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...