The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...

The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...

If the ARM processor in its many incarnations is to take on the reigning Xeon champ in the datacenter and the born again Power processor that is also trying to knock Xeons from the throne, it is going ...

The ARM9-based LTC3180 combines 208-MHz, 228-MIPS performance with fine-tuned power control. Rule number one for designers of portables: Optimize the power usage in embedded applications for long ...

Since its proposal back in 1991 by Joe Mitola in a landmark paper on thesubject, the notion of Software Defined Radio (SDR) has captured theimagination of wireless design engineers in both government ...

Eran Briman, vice president of marketing at CEVA, commented: “The CEVA-XC4500 DSP is a game-changer for wireless infrastructure applications, combining powerful fixed- and floating-point vector ...

In a world in which multiple sensors are being designed into almost everything, processing of all the data inputs, or sensor fusion, is becoming an increasingly important part of the system. To ...

- Gen4 CEVA-XC architecture offers highest performance of 1,600 GOPS, innovative dynamic multithreading and advanced pipeline to reach operating speeds of 1.8GHz at 7nm - CEVA-XC16, first processor ...

A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that ...